Patents


  1. "Quantum Well Wire Structures," J. Cibert, A.C. Gossard, S.J. Pearton and P.M. Petroff, Issued June 14, 1988, U.S. Patent 4,751 194.
  2. "Fabrication of Semiconductor Devices without Breaking Vacuum," A. Katz and S.J. Pearton, Patent Submission 104991 (1992).
  3. "Method for Reducing Sidewall Roughness During Dry Etching," C. Abernathy, J. Lothian, S.J. Pearton and F. Ren, Patent Submission 105336 (1992).
  4. "GaAs Device Fabrication Utilizing MOMBE" Abernathy, Hobson, Jordan, Pearton and Ren, (Feb. 1991), US Patent 5171704.
  5. "Self-aligned Dry Etch Process for In-based HBTs," Fullowan, Pearton and Ren, Issued December 1, 1992: U.S. Patent 5, 168 071.
  6. "Method for Forming Patterned W Layers," Fullowan, Pearton and Ren, Issued January 5, 1993: U.S. Patent 5,176 792; European Patent 92309607.
  7. "Method for Selectively Growing Ga-containing Layers," Abernathy, Pearton, Ren and Wisk, Issued July 13, 1993: U.S. Patent 5,227 006; European Patent 92310488.
  8. "Method for Making Fine-line Semiconductor Devices," Abernathy, Lothian, Pearton and Ren, European Patent 94301125 (April 20, 1994).
  9. "Method for Selectively Growing Al-containing Layers," Abernathy, Pearton, Ren and Wisk: European Patent 92310487 (1993): U.S. Patent 5,459 097.
  10. "Fabrication of Al-containing Semiconductor Devices," Abernathy, Hobson, Jordan, Pearton and Ren: European Patent 92301438 (1992).
  11. “GaN-type enhancement MOSFET using heterostructure”, Abernathy, Irokawa, Pearton and Ren, US Patent 6,914,273(2005).
  12. “Semiconductor Device and Method using Nanotube Contacts,” A.G. Rinzler and S.J. Pearton, Patent Disclosure UF 11481, February 2004, European Patent No. 1719155(2006)


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